1. Field of the Invention
The present invention relates to interconnect layers and contacts in a semiconductor. More specifically, it relates to a semiconductor memory including an extended region, extended from a cell array, in which interconnects are formed at a fine pitch. A control gate, a metallic interconnect, a bit line pattern, or related patterns are formed with non-uniform patterns in such extended region.
2. Description of the Related Art
Diagonal interconnects are conventionally used in extended regions of a semiconductor memory. More specifically, diagonal interconnects are used to provide a longer pitch in a region extending to contacts. However, as miniaturization advances, cells are being miniaturized by forming patterns with high resolution in only a single direction through double exposure. This brings about needs to form all cell patterns with lines and spaces at regular intervals. Therefore, it is impossible to form a non-uniform pattern in the extended region. This problem brings about needs to form contacts within such a pattern of lines and spaces not including such contact formation patterns.
Japanese Patent Application Laid-open No. Hei 9-97882 (FIGS. 37 and 39) discloses a semiconductor device and a fabrication method thereof for forming contacts with diffusion layers by use of self-aligned polysilicon and polysilicon plugs formed in an array-shaped active region of a DRAM after formation of device isolating regions, rather than forming contacts with gate interconnect patterns or the like.